基本释义:

设陷指令

网络释义

1)trapped instruction,设陷指令

2)trap instruction,陷阱指令

3)commander equipment,指令设备

4)software trap instruction,软件陷阱指令

5)design of microinstruction,微指令设计

6)instruction cache design,指令Cache设计

用法和例句

This paper analyzes the traditional instruction prefetch technologies,studies a new instruction prefetch technology based on the communications between compilers and processors with the Explicitly Parallel Instruction Computing architecture, and gives a L1 instruction cache design scheme supporting several technologies.

本文分析了传统的指令预取技术,并结合显性指令并行计算(EPIC)体系结构,研究了基于编译器与处理器通信的新的指令预取技术,提出了一种支持多种预取技术的L1指令Cache设计方案。

Designed technology of instruction cache based on pipeline;

基于流水线的指令Cache设计技术

Design and System-level Verification of Instruction CACHE Architure;

指令CACHE结构设计与系统级验证

Vector Instruction Set Optimized for Cache

面向Cache优化的向量指令集设计与测评

The Research and Design of Cache Controller;

Cache Controller的研究和设计

An I-cache Attack Method on RSA Implementation

针对RSA密码算法的指令Cache攻击方法

Study and Implement on Code Reordering Technology of I-Cache Optimization;

指令Cache优化中代码重排技术的研究与实现

Synchronization technology based on invalidation of instruction Cache for multi-core processor

基于指令Cache作废的多核处理器同步技术

Design and Verification of Data Cache Bank;

数据Cache存储体的设计与验证

Design and Verification for the Cache Based on ARM7TDMI;

基于ARM7TDMI的Cache的设计与验证

Full Custom Design and Verification of Data Cache Tag;

数据Cache Tag的全定制设计与验证

Cache Simulation System Design in Linux;

基于Linux的Cache模拟系统设计

Research on Design and Verification of Cache for a 32-bit DSP;

一种32位DSP cache的设计与验证技术研究

The Optimation Design Two Level Cache Controller on YHFT-DX Chip

YHFT-DX片内二级Cache控制器的优化设计

Cache Research and Design for Embedded Processors

嵌入式处理器中Cache的研究与设计

Design and Implementation of Level One Cache Miss Pipelining on High Performance DSP

高性能DSP一级Cache缺失流水设计与实现

Research and Design of Low-Power Cache in Embedded Systems

嵌入式系统中低功耗Cache的研究与设计

Full Custom Design and Realization of SRAM in L2 Cache Tag

二级Cache Tag中SRAM的全定制设计与实现

Design of Cache Miss Pipelining in YHFT-DX High Performance DSP

YHFT-DX高性能DSP中Cache失效流水设计