基本释义:

行译码器

网络释义

1)row decoder,行译码器

2)block parallel decoder,分块并行译码器

3)parallel BCH decoder,并行BCH译码器

4)serial digital decoder,串行数字译码器

5)quasi-parallel decoder,准并行译码器

6)parallel decoder,全并行译码器

用法和例句

Design and implementation of a full parallel LDPC decoder

LDPC码全并行译码器的设计与实现

The interpretation is carried out by the instruction decoder.

该翻译借指令译码器来进行。

Design and Implementation of Hign Throughput Parallel Turbo Decoder;

高速并行Turbo译码器的设计与实现

FPGA Implementation of a Novel Parallel Turbo Encoder/Decoder;

一种新型并行Turbo编译码器的FPGA实现

Design and Implementation of Configurable Parallet BCH Decoder

可配置并行BCH译码器的设计与实现

Design and Realization of Improved All-parallel Viterbi Decoder

改进型全并行Viterbi译码器设计与实现

High-Speed Parallel BCH Decoder Circuit in VLSI

高速并行BCH译码器的VLSI设计

Christmas tree type decoder

“圣诞树”型译码器

The CODEC can be used to carry on coding transmission and decoding reception in parallel with code error detection and bit synchronized signal recovering.

该编译码器能进行并行发送编码和接收译码,并带有误码检测和位同步提取的功能。

FPGA Implementation of SOVA-Based Turbo Decoder;

Turbo码SOVA译码器FPGA实现

Joint Optimization of Linear Precoders and Decoders for Multiuser MIMO Downlink

多用户MIMO下行链路中线性预编码器和译码器的联合优化

Dimidiate Window Improving and FPGA Implementation of Series Turbo Decoder

串行Turbo译码器窗口二分法改进与FPGA实现

To convert(a character, routine, or program) into machine language.

编码，译码将（字符、例行程序或程序）转变为机器语言

Research on Construction, Parallel Concatenation and Decoder Design of Low-Density Parity-Check Codes;

低密度奇偶校验码构造、并行级联与译码器设计的研究

A Serial-structured Viterbi Decoder Design for(2,1,7)Convolution Code on FPGA

一种串行结构的2,1,7卷积码维特比译码器的FPGA实现

Design and implementation of a high-throughput decoder for multi-rate LDPC code

多码率LDPC码高速译码器的设计与实现

Optimized Decoder Design and Implement for High Rate LDPC Codes

高码率LDPC码译码器的优化设计与实现

The Signal Generator and Encoder of Bark Code Based on CPLD;

基于CPLD的巴克码信号发生器与译码器