基本释义:

帧同步丢失

网络释义

1)LFS Loss of Frame Synchronization,帧同步丢失

2)Frame Alignment Loss FAL,帧同步丢失

3)frame synchronization,帧同步

4)frame synchronization code,帧同步码

5)frame synchronizer,帧同步器

6)frame synchronous,帧同步

7)Frame Synchronizer,帧同步机

8)frame-synchronization,帧同步

9)frame synchronizing word,帧同步字

10)frame aligner,帧同步器

用法和例句

A frame synchronization algorithm based on IEEE802.11a WLAN standard;

基于802.11a的帧同步算法研究

Maximum A Posteriori-based frame synchronization algorithm;

基于最大后验概率的帧同步判决

Design and implementation of an FPGA-based PCM frame synchronization detection and alarm system;

基于FPGA的PCM帧同步检测及告警电路的设计

We combine the error-tolerant technology with no error-tolerant technology to carry out the detection of the frame synchronization code.

提出一种数字传输系统中帧同步码的检测方案 ,利用容错技术和非容错技术相结合来实现帧同步码检测 。

Design and implementation of the frame synchronizer with adaptive phase based on synchronization state machine;

基于状态机自适应相位帧同步器的设计与实现

A new frame synchronizer for turbo code based on the fusion of two kinds of information is proposed in this paper.

提出了一种基于两种信息融合的turbo码帧同步器。

A frame synchronizer with recognizer and discriminator is described, which consists mainlyof a type 8951 singlechip computer, a type 8254 programmable counter and a GAL chip.

在激光水下通信的节头内插入捕获序列，用８９５１，８２５４，ＧＡＬ等芯片构成识别判决式帧同步器。

The FPGA Design of AOS Frame Synchronous Transmitter Based on PCI Bus;

基于PCI总线的高级在轨系统帧同步信号发送器的FPGA设计

But in the hardware design phase,there was few I/O pin can be used,so don t have the frame synchronous signal in communication,only the clock control signal and the serial data signal were used in receiving the GPS serial data frame.

该电子产品的功能是接收来自某GPS接收机发送的GPS串行数据帧,然后对数据进行识别与处理;但在硬件设计时由于I/O口资源使用紧张,使得接收GPS串行数据帧时只有时钟控制信号与串行数据信号,而没有帧同步信号,这样在软件实现时对于识别出正确的数据帧造成了很大的困难,在软件设计时利用GPS串行数据帧中数据自身以及通信协议中的一些特殊性来对无帧同步信号的串行数据进行识别与处理。

Based on the analysis to PCM30/32 basic group s frame structure and the structure and function of frame synchronous circuit,the chapter has designed with VHDL the frame synchronous circuit with up-down method of modern electronic designing by using EDA simunation software Modelsim SE 5.

帧同步电路是数字通信系统中的重要组成部分。

Study and Implementation of Frame Synchronizer Based on FPGA;

基于FPGA的帧同步机设计与实现

Design and Implement of Frame Synchronizer;

一种帧同步机的实用设计

5 V is how to achieve code-synchronization and frame-synchronization.

5 VPCM码流解码的关键是码同步和帧同步的实现。

To solve these issues,this paper proposes three new methods that include digital CDR,parallel bit-synchronization and parallel error-tolerance frame-synchronization.

本文结合新型高速光纤传输系统的研制,从物理层、链路层、数据层的角度出发,提出了数字化高速时钟恢复、并行比特同步、并行容错帧同步的组合设计方案,有效地减少了同步时间,提高了光纤系统数据传输效率,并成功应用于特种设备领域,取得了很好的效益。

The key is how to implement hardware synchronization, concludes clock-synchronization, code-synchronization and frame-synchronization.

该电路设计的关键是实现硬件同步,包括时钟同步、码同步和帧同步,并进行串并转换完成对高速PCM码的解调。

In the process of data transmission,the most important is data synchronous transmission,it needs insert frame synchronizing word in the data and testing it with digial correlation device in the process of data transmission.

在数字通信的数据传输过程中,需要保持数据在传输过程中的同步,因此要在数据传输过程中插入帧同步字并用数字相关器对帧同步字进行检测,从而有效地避免发送数据与接收数据在传输过程中出现的异步问题。

Parameters of this frame aligner are selected based on the ana-lyzing of system performances.

介绍了SDH系统中的帧同步器的设计思想,依据ITU-T关于SDH技术体制的建议,分析并计算了STM-1帧同步器的几个重要参数,选择了合适的帧同步码组。

The design of high speed SDH frame aligner is introduced in this paper, and the relation between frame aligner performances and the parameters is also analyzed.

介绍了高速 SDH系统中的帧同步器的设计 ,分析了影响帧同步器性能的参数选择。